A sample and hold circuit is usually employed in the front end of high speed flash and folding analog-to-digital (A/D) converters. Such A/D converters are widely used in modern communications and data storage integrated circuits. In such applications, the sample and hold (S/H) (either sample and hold or track and hold) circuit must drive a large array of comparators. This presents a large load capacitance and requires a high speed buffer amplifier at the output of the S/H circuit.
The circuit schematic diagram of a conventional prior art buffer amplifier suitable for high speed applications is shown in FIG. 1. Two such buffers are typically used in a differential S/H circuit as shown in FIG. 2, one buffer for the positive terminal (Vinp) of the input and one for the negative terminal (Vinn) of the input. The buffer amplifier as shown in FIG. 1 includes a simple differential amplifier M1 and M2 followed by source follower (transistor M7). The input Vb provides bias current for the entire amplifier. The simplicity of the circuit results in a high speed of operation. However, at low supply voltages, this circuit suffers from two problems: 1) there is insufficient headroom (voltage lower than the supply voltage) for the operation of the source follower transistor M7 and 2) it to ensure that the tail current source, the current through transistor M4, is sufficiently deep into saturation at the full swing of the input signal. This results in a modulation of the tail current, causing harmonic distortion.
It is therefore readily apparent that there is a need for a buffer amplifier circuit usable for high speed S/H applications that addresses and minimizes the above described problems inherent in the prior art circuits.